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d a t a sh eet product speci?cation supersedes data of 1998 dec 11 file under integrated circuits, ic24 2000 mar 09 integrated circuits 74avc16373 16-bit d-type transparent latch; 3.6 v tolerant; 3-state
2000 mar 09 2 philips semiconductors product speci?cation 16-bit d-type transparent latch; 3.6 v tolerant; 3-state 74avc16373 features wide supply voltage range from 1.2 to 3.6 v complies with jedec standard no. 8-1a/5/7 cmos low power consumption input/output tolerant up to 3.6 v dynamic controlled output (dco) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation low inductance multiple v cc and gnd pins to minimize noise and ground bounce supports live insertion. description the 74avc16373 is a 16-bit d-type transparent latch featuring separate d-type inputs for each latch, and 3-state outputs for bus oriented applications. one latch enable (le) input and one output enable ( oe) input are provided per 8-bit section. the 74avc16373 consist of two sections of eight d-type transparent latches with 3-state true outputs. the 74avc16373 is designed to have an extremely fast propagation delay and a minimum amount of power consumption. to ensure the high-impedance output state during power-up or power-down, pin oe n should be tied to v cc through a pull-up resistor (live insertion). a dynamic controlled output (dco) circuitry is implemented to support termination line drive during transient (see figs 1 and 2). handbook, halfpage 012 4 0 - 200 - 300 - 100 mna506 3 v oh (v) i oh (ma) 1.8 v 2.5 v 3.3 v fig.1 output voltage as a function of the high-level output current. handbook, halfpage 012 4 300 100 0 200 mna507 3 v ol (v) i ol (ma) 1.8 v 2.5 v 3.3 v fig.2 output voltage as a function of the low-level output current.
2000 mar 09 3 philips semiconductors product speci?cation 16-bit d-type transparent latch; 3.6 v tolerant; 3-state 74avc16373 quick reference data gnd = 0 v; t amb =25 c; t r =t f 2.0 ns. notes 1. c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i + ? (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; ? (c l v cc 2 f o ) = sum of outputs. 2. the condition is v i = gnd to v cc . function table see note 1. note 1. h = high voltage level; h = high voltage level one set-up time prior to the high-to-low le transition; l = low voltage level; l = low voltage level one set-up time prior to the high-to-low le transition; z = high impedance off-state. symbol parameter conditions typ. unit t phl /t plh propagation delay nd n to nq n v cc = 1.2 v 3.6 ns v cc = 1.5 v 3.1 ns v cc = 1.8 v 2.2 ns v cc = 2.5 v 1.6 ns v cc = 3.3 v 1.4 ns c i input capacitance 5.0 pf c pd power dissipation capacitance per buffer notes 1 and 2 outputs enabled 34 pf outputs disabled 1 pf operating modes inputs internal latches outputs n oe le na n ny n enable and read register (transparent mode) l l h h l h l h l h latch and read register (hold mode) l l l l l h l h l h latch register and disable outputs h h l l l h l h z z
2000 mar 09 4 philips semiconductors product speci?cation 16-bit d-type transparent latch; 3.6 v tolerant; 3-state 74avc16373 ordering and package information pinning type number package temperature range pins package material code 74avc16373dgg - 40 to +85 c 48 tssop plastic sot362-1 pin symbol description 11 oe output enable input (active low) 2, 3, 5, 6, 8, 9, 11 and 12 1q 0 to 1q 7 data outputs 4, 10, 15, 21, 28, 34, 39 and 45 gnd ground (0 v) 7, 18, 31 and 42 v cc dc supply voltage 13, 14, 16, 17, 19, 20, 22 and 23 2q 0 to 2q 7 data outputs 24 2 oe output enable input (active low) 25 2le latch enable input (active high) 26, 27, 29, 30, 32, 33, 35 and 36 2d 7 to 2d 0 data inputs 37, 38, 40, 41, 43, 44, 46 and 47 1d 7 to 1d 0 data inputs 48 1le latch enable input (active high)
2000 mar 09 5 philips semiconductors product speci?cation 16-bit d-type transparent latch; 3.6 v tolerant; 3-state 74avc16373 handbook, halfpage 16373 mna541 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1oe 1q 0 1q 1 gnd 1q 2 1q 3 v cc 1q 4 1q 5 gnd 1q 6 1q 7 2q 0 2q 1 gnd 2q 2 2q 3 v cc 2q 4 2q 5 gnd 2q 6 2q 7 2oe 1le 1d 0 1d 1 gnd 1d 2 1d 3 v cc 1d 4 1d 5 gnd 1d 6 1d 7 2d 0 2d 1 gnd 2d 2 2d 3 v cc 2d 4 2d 5 gnd 2d 6 2d 7 2le 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 fig.3 pin configuration. handbook, halfpage mna547 1q 0 1q 1 1le 2le 1q 2 1q 3 1q 4 1q 5 1q 6 1q 7 1oe 47 46 48 25 44 43 41 40 38 37 2 3 1 5 6 8 9 11 12 24 2q 0 2q 1 2q 2 2q 3 2q 4 2q 5 2q 6 2q 7 1d 0 1d 1 1d 2 1d 3 1d 4 1d 5 1d 6 1d 7 2d 0 2d 1 2d 2 2d 3 2d 4 2d 5 2d 6 2d 7 36 35 33 32 30 29 27 26 13 14 16 17 19 20 22 23 2oe fig.4 logic symbol.
2000 mar 09 6 philips semiconductors product speci?cation 16-bit d-type transparent latch; 3.6 v tolerant; 3-state 74avc16373 handbook, halfpage 23 mna546 37 12 11 9 8 6 5 47 46 44 43 41 40 38 1d 7 1d 0 1d 1 1d 2 1d 3 1d 4 1d 5 1d 6 2 3 1q 7 1q 6 1q 5 1q 4 1q 3 1q 2 1q 0 1q 1 26 22 20 19 17 16 36 35 33 32 30 29 27 2d 5 2d 0 2d 1 2d 2 2d 3 2d 4 13 14 2q 5 2q 4 2q 3 2q 2 2q 1 2q 0 24 25 2en 1oe 1 1en 1le 2oe 2le 48 c3 c4 3d 1 4d 2 2d 7 2d 6 2q 7 2q 6 fig.5 ieee/iec logic symbol. handbook, full pagewidth mna545 d1q 0 1d 0 1le 1oe q le latch 1 to 7 other channels d2q 0 2d 0 2le 2oe q le latch 9 to 7 other channels fig.6 logic diagram.
2000 mar 09 7 philips semiconductors product speci?cation 16-bit d-type transparent latch; 3.6 v tolerant; 3-state 74avc16373 recommended operating conditions limiting values in accordance with the absolute maximum rating system (iec 60134); voltages are referenced to gnd (ground = 0 v). notes 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. above 60 c the value of p d derates linearly with 5.5 mw/k. symbol parameter conditions min. max. unit v cc dc supply voltage according to jedec low voltage standards 1.4 1.6 v 1.65 1.95 v 2.3 2.7 v 3.0 3.6 v for low-voltage applications 1.2 3.6 v v i dc input voltage 0 3.6 v v o dc output voltage output 3-state 0 3.6 v output high or low state 0 v cc v t amb operating ambient temperature in free air - 40 +85 c t r ,t f input rise and fall time ratios v cc = 1.4 to 1.6 v 0 40 ns/v v cc = 1.65 to 2.3 v 0 30 ns/v v cc = 2.3 to 3.0 v 0 20 ns/v v cc = 3.0 to 3.6 v 0 10 ns/v symbol parameter conditions min. max. unit v cc dc supply voltage - 0.5 +4.6 v i ik dc input diode current v i <0 -- 50 ma v i dc input voltage for inputs; note 1 - 0.5 +4.6 v i ok dc output clamping diode current v o <0 -- 50 ma v o dc output voltage output high or low state; note 1 - 0.5 v cc + 0.5 v output 3-state; note 1 - 0.5 +4.6 v i o dc output sink current v o = 0 to v cc - 50 ma i cc ,i gnd dc v cc or gnd current - 100 ma t stg storage temperature - 65 +150 c p d power dissipation per package for temperature range: - 40 to +85 c; note 2 - 500 mw
2000 mar 09 8 philips semiconductors product speci?cation 16-bit d-type transparent latch; 3.6 v tolerant; 3-state 74avc16373 dc characteristics over recommended operating conditions; voltages are referenced to gnd (groun d=0v). note 1. all typical values are measured at t amb =25 c. symbol parameter test conditions t amb = - 40 to +85 c unit other v cc (v) min. typ. (1) max. v ih high-level input voltage 1.2 v cc -- v 1.4 to 1.6 0.65 v cc 0.9 - v 1.65 to 1.95 0.65 v cc 0.9 - v 2.3 to 2.7 1.7 1.2 - v 3.0 to 3.6 2.0 1.5 - v v il low-level input voltage 1.2 -- gnd v 1.4 to 1.6 - 0.9 0.35 v cc v 1.65 to 1.95 - 0.9 0.35 v cc v 2.3 to 2.7 - 1.2 0.7 v 3.0 to 3.6 - 1.5 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 100 m a 1.65 to 3.6 v cc - 0.20 v cc - v i o = - 3 ma 1.4 v cc - 0.35 v cc - 0.23 - v i o = - 4 ma 1.65 v cc - 0.45 v cc - 0.25 - v i o = - 8 ma 2.3 v cc - 0.55 v cc - 0.38 - v i o = - 12 ma 3.0 v cc - 0.70 v cc - 0.48 - v v ol low-level output voltage v i =v ih or v il i o = 100 m a 1.65 to 3.6 - gnd 0.20 v i o =3ma 1.4 - 0.18 0.35 v i o = 4 ma 1.65 - 0.22 0.45 v i o =8ma 2.3 - 0.37 0.55 v i o =2ma 3.0 - 0.51 0.70 v i i input leakage current per pin v i =v cc or gnd 1.4 to 3.6 - 0.1 2.5 m a i off power-off leakage current v i or v o = 3.6 v 0 - 0.1 10 m a i ihz /i ilz input current for common i/o pins v i =v cc or gnd 1.4 to 3.6 - 0.1 12.5 m a i oz 3-state output off - state current v i =v ih or v il ; v o =v cc or gnd 1.4 to 2.7 - 0.1 5 m a 3.0 to 3.6 - 0.1 10 m a i cc quiescent supply current v i =v cc or gnd; i o =0 1.4 to 2.7 - 0.1 20 m a 3.0 to 3.6 - 0.2 40 m a
2000 mar 09 9 philips semiconductors product speci?cation 16-bit d-type transparent latch; 3.6 v tolerant; 3-state 74avc16373 ac characteristics gnd = 0 v; t r =t f 2.0 ns. note 1. all typical values are measured at t amb =25 c and at v cc respectively 1.2, 1.5, 1.8, 2.5 and 3.3 v. symbol parameter test conditions t amb = - 40 to +85 c unit waveforms v cc (v) min. typ. (1) max. t phl /t plh propagation delay nd n to nq n see figs 7 and 11 1.2 - 3.6 - ns 1.40 to 1.60 1.2 3.1 6.8 ns 1.65 to 1.95 1.0 2.2 5.7 ns 2.3 to 2.7 0.7 1.6 3.3 ns 3.0 to 3.6 0.7 1.4 2.8 ns propagation delay nle to nq n see figs 8 and 11 1.2 - 3.6 - ns 1.40 to 1.60 2.5 3.1 9.4 ns 1.65 to 1.95 2.3 2.2 7.8 ns 2.3 to 2.7 1.3 1.6 4.2 ns 3.0 to 3.6 0.7 1.4 3.9 ns t pzh /t pzl 3-state output enable time n oe to nq n see figs 9 and 11 1.2 - 5.9 - ns 1.40 to 1.60 1.6 4.2 8.8 ns 1.65 to 1.95 1.6 3.5 6.7 ns 2.3 to 2.7 1.4 2.4 4.3 ns 3.0 to 3.6 0.7 2.0 3.4 ns t phz /t plz 3-state output disable time n oe to nq n see figs 9 and 11 1.2 - 5.8 - ns 1.40 to 1.60 2.5 4.6 9.4 ns 1.65 to 1.95 2.3 3.6 7.8 ns 2.3 to 2.7 1.3 1.9 4.2 ns 3.0 to 3.6 1.2 2.1 3.9 ns t w nle pulse width high see figs 8 and 11 1.2 - 2.4 - ns 1.40 to 1.60 - 1.9 - ns 1.65 to 1.95 2.2 1.7 - ns 2.3 to 2.7 2.0 1.6 - ns 3.0 to 3.6 1.8 1.4 - ns t su set-up time nd n to nle see figs 10 and 11 1.2 - 0.4 - ns 1.40 to 1.60 1.2 0.2 - ns 1.65 to 1.95 1.1 0.1 - ns 2.3 to 2.7 +0.9 - 0.1 - ns 3.0 to 3.6 +0.8 - 0.1 - ns t h hold time nd n to nle see figs 10 and 11 1.2 -- 0.2 - ns 1.40 to 1.60 +1.1 - 0.1 - ns 1.65 to 1.95 1.1 0.0 - ns 2.3 to 2.7 1.1 0.1 - ns 3.0 to 3.6 1.0 0.2 - ns
2000 mar 09 10 philips semiconductors product speci?cation 16-bit d-type transparent latch; 3.6 v tolerant; 3-state 74avc16373 ac waveforms handbook, full pagewidth mna544 t plh t phl v m v m nq n output nd n input gnd v i v oh v ol fig.7 the input (nd n ) to output (nq n ) propagation delay. v cc v m v i 2.3 to 2.7 v 0.5 v cc v cc 3.0 to 3.6 v 0.5 v cc v cc v ol and v oh are typical output voltage drop that occur with the output load. handbook, full pagewidth mna543 t phl t plh t w v m v m v m nle input nq n output gnd v i v oh v ol fig.8 the latch enable input (nle) pulse width to output (nq n ) propagation delays. v cc v m v i 2.3 to 2.7 v 0.5 v cc v cc 3.0 to 3.6 v 0.5 v cc v cc v ol and v oh are typical output voltage drop that occur with the output load.
2000 mar 09 11 philips semiconductors product speci?cation 16-bit d-type transparent latch; 3.6 v tolerant; 3-state 74avc16373 handbook, full pagewidth mna478 t plz t phz outputs disabled outputs enabled v y v x outputs enabled output low-to-off off-to-low output high-to-off off-to-high noe input v i v ol v oh v cc v m gnd gnd t pzl t pzh v m v m fig.9 3-state enable and disable times. v cc v m v x v y v i 2.3 to 2.7 v 0.5 v cc v ol + 0.15 v v oh - 0.15 v v cc 3.0 to 3.6 v 0.5 v cc v ol + 0.3 v v oh - 0.3 v v cc v ol and v oh are typical output voltage drop that occur with the output load. handbook, full pagewidth mna542 t h t su t h t su v m v m v i gnd v i gnd nle input nd n input fig.10 data set-up and hold times for nd n input to nle input. v cc v m v i 2.3 to 2.7 v 0.5 v cc v cc 3.0 to 3.6 v 0.5 v cc v cc the shaded areas indicate when the input is permitted to change for predictable output performance.
2000 mar 09 12 philips semiconductors product speci?cation 16-bit d-type transparent latch; 3.6 v tolerant; 3-state 74avc16373 handbook, full pagewidth open gnd 2 v cc v cc v i v o mna505 d.u.t. c l r t r load r load pulse generator s1 fig.11 load circuitry for switching times. test s1 t plh /t phl open t plz /t pzl 2 v cc t phz /t pzh gnd v cc (v) v i r load c l 1.2 v cc 2000 w 15 pf 1.4 to 1.6 v cc 2000 w 15 pf 1.65 to 1.95 v cc 1000 w 30 pf 2.3 to 2.7 v cc 500 w 30 pf 3.0 to 3.6 v cc 500 w 30 pf
2000 mar 09 13 philips semiconductors product speci?cation 16-bit d-type transparent latch; 3.6 v tolerant; 3-state 74avc16373 package outline unit a 1 a 2 a 3 b p cd (1) e (2) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0.05 0.2 0.1 8 0 o o 0.1 dimensions (mm are the original dimensions). notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. sot362-1 95-02-10 99-12-27 w m q a a 1 a 2 d l p q detail x e z e c l x (a ) 3 0.25 124 48 25 y pin 1 index b h 1.05 0.85 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 1 0.25 8.3 7.9 0.50 0.35 0.8 0.4 0.08 0.8 0.4 p e v m a a tssop48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1 a max. 1.2 0 2.5 5 mm scale mo-153
2000 mar 09 14 philips semiconductors product speci?cation 16-bit d-type transparent latch; 3.6 v tolerant; 3-state 74avc16373 soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2000 mar 09 15 philips semiconductors product speci?cation 16-bit d-type transparent latch; 3.6 v tolerant; 3-state 74avc16373 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2000 69 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 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